View SAA7335_143966.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAA7335 DSP for CD and DVD-ROM systems
Preliminary specification File under Integrated Circuits, IC01 1997 Aug 11
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
FEATURES * Compatibility with CD-I, CD-ROM, MPEG-video DVD-ROM and DVD-video applications * Designed for very high playback speeds * Typical CD-ROM operation up to n = 12, DVD-ROM to n = 1.9, maximum rates (tbf) * Matched filtering, quad-pass error correction (C1-C2-C1-C2), overspeed audio playback function included (up to 3 kbytes buffer) * Lock-to-disc playback, Constant Angular Velocity (CAV), pseudo-Constant Linear Velocity (CLV) and CLV motor control loops * Interface to 32 kbytes SRAM for DVD error correction and de-interleave * Sub-code/ header processing for DVD and CD formats * Programmable HF equalizer * In DVD mode it is still compatible with Philips block decoders * Sub-CPU interface can be parallel or fast I2C-bus * On-chip clock multiplier. GENERAL DESCRIPTION This device is a high-end combined Compact Disc (CD) and Digital Versatile Disc (DVD) compatible decoding device. The device operates with an external 32 kbytes S-RAM memory for de-interleaving operations. The device provides quad-pass error correction for CD-ROM applications (C1-C2-C1-C2) and operates in lock-to-disk, CAV, pseudo CLV and CLV modes. QUICK REFERENCE DATA SYMBOL VDDD IDDD VDDA IDDA fxtal Tamb Tstg PARAMETER digital supply voltage digital supply current analog supply voltage analog supply current crystal input frequency operating ambient temperature storage temperature - 4.5 - 4 -20 -55 MIN. 4.5 70 5.0 70 25 - - TYP. 5.0
SAA7335
In DVD modes double-pass C1-C2 error correction is used which is capable of correcting up to 5 C1 frame errors and 16 C2 frame errors. The SAA7335 contains all the functions required to decode an EFM or EFM+ HF signal directly from the laser pre-amplifier, including analog front-end, PLL data recovery, demodulation and error correction. The spindle motor interface provides both motor control signals from the demodulator and, in addition, contains a tachometer loop that accepts tachometer pulses from the motor unit. The SAA7335 has two independent microcontroller interfaces. The first is a serial I2C-bus and the second is a standard 8-bit multiplexed parallel interface. Both of these interfaces provide access to a total of 32 x 8-bit registers for control and status. This data sheet contains an descriptive overview of the device together with electrical and timing characteristics. For a detailed description of the device refer to the user guide "SAU/UM96018". Supply of this CD/DVD IC does not convey an implied license under any patent right to use this IC in any CD or DVD application.
MAX. 5.5 300 5.5 300 tbf +70 +125 V
UNIT mA V mA MHz C C
1997 Aug 11
2
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
ORDERING INFORMATION TYPE NUMBER SAA7335GP PACKAGE NAME LQFP100 DESCRIPTION
SAA7335
VERSION SOT407-1
plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
BLOCK DIAGRAM
handbook, full pagewidth
SRAM 32 KBYTES
HF input
ADC
PLL BIT DETECTOR
DEMODULATOR EFM/EFM+ DECODER I2S-BUS OUTPUT INTERFACE block decoder output
clock input
CLOCK GENERATOR
SPINDLE MOTOR CONTROL
SAA7335
SUB-CPU INTERFACE
MGK242
motor control
Fig.1 Simplified block diagram.
1997 Aug 11
3
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
PINNING SYMBOL VSSA1 Iref REFLo REFHi VREF HFIN VSSA2 AGCOUT VDDA2 VDDD1 VSSD1 OTD MOTO1 n.c. MOTO2/T3 n.c. T1 T2 VDDD2 VSSD2 TEST1 TEST2 POR MUXSWICH n.c. CL1 BCAIN SDA SCL INT VDDD3 VSSD3 da7 da6 da5 n.c. da4 n.c. da3 da2 1997 Aug 11 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TYPE supply I I I I I supply O supply supply supply I O - I/O - I I supply supply I I I I - O I I/O I O supply supply I/O I/O I/O - I/O - I/O I/O analog ground 1 analog current reference input for ADC analog low reference input for ADC analog high reference input for ADC analog negative input analog positive input analog ground 2 analog test pin output analog supply voltage 2 digital supply voltage 1 digital ground 1 off track detect input 3-state motor control output not connected, reserved motor control output/tachometer 3 input not connected, reserved tachometer 1 input tachometer 2 input digital supply voltage 2 digital ground 2 test input 1 test input 2 power-on reset input use clock multiplier input not connected, reserved divided clock output BCA input sub-CPU I2C-bus serial data input/output sub-CPU I2C-bus serial clock input sub-CPU interrupt output (open-drain) digital supply voltage 3 digital ground 3 sub-CPU data bus bit 7 input/output (parallel) sub-CPU data bus bit 6 input/output (parallel) sub-CPU data bus bit 5 input/output (parallel) not connected, reserved sub-CPU data bus bit 4 input/output (parallel) not connected, reserved sub-CPU data bus bit 3 input/output (parallel) sub-CPU data bus bit 2 input/output (parallel) 4 DESCRIPTION
SAA7335
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
SYMBOL da1 n.c. da0 VDDD4 VSSD4 WRi RDi ALE CSi STOPCLOCK n.c. V4 EBUOUT SYNC FLAG DATA BCLK WCLK VDDD5 VSSD5 RAMRW n.c. RAMDA7 RAMDA6 RAMDA5 RAMDA4 RAMDA3 RAMDA2 n.c. RAMDA1 RAMDA0 VDDD6 VSSD6 RAMAD0 RAMAD1 RAMAD2 RAMAD3 RAMAD4 RAMAD5 RAMAD6 VDDD7 1997 Aug 11
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
TYPE I/O - I/O supply supply I I I I O - O O O O O I/O I/O supply supply O - I/O I/O I/O I/O I/O I/O - I/O I/O supply supply O O O O O O O supply not connected, reserved
DESCRIPTION sub-CPU data bus bit 1 input/output (parallel) sub-CPU data bus bit 0 input/output (parallel) digital supply voltage 4 digital ground 4 sub-CPU write enable input (active LOW) sub-CPU read enable input (active LOW) sub-CPU address latch enable input sub-CPU chip select input (active HIGH) stop clock output not connected, reserved serial subcode output (for CD) digital audio output I2S-bus sector sync output I2S-bus correction flag output I2S-bus serial data output I2S-bus bit serial clock input/output I2S-bus word clock input/output digital supply voltage 5 digital ground 5 RAM read/write control output not connected, reserved RAM data bus bit 7 input/output RAM data bus bit 6 input/output RAM data bus bit 5 input/output RAM data bus bit 4 input/output RAM data bus bit 3 input/output RAM data bus bit 2 input/output not connected, reserved RAM data bus bit 1 input/output RAM data bus bit 0 input/output digital supply voltage 6 digital ground 6 RAM address bit 0 output RAM address bit 1 output RAM address bit 2 output RAM address bit 3 output RAM address bit 4 output RAM address bit 5 output RAM address bit 6 output digital supply voltage 7 5
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
SYMBOL VSSD7 RAMAD7 RAMAD8 RAMAD9 n.c. RAMAD10 RAMAD11 RAMAD12 RAMAD13 RAMAD14 VDDD8 VSSD8 CRIN CROUT CFLG MEAS1 VDDD9 VSSD9 VDDA1
PIN 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
TYPE supply O O O - O O O O O supply supply I O O O supply supply supply digital ground 7
DESCRIPTION RAM address bit 7 output RAM address bit 8 output RAM address bit 9 output not connected, reserved RAM address bit 10 output RAM address bit 11 output RAM address bit 12 output RAM address bit 13 output RAM address bit 14 output digital supply voltage 8 digital ground 8 analog crystal input analog crystal output correction statistics output front-end telemetry output digital supply voltage 9 digital ground 9 analog supply voltage 1
1997 Aug 11
6
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
91 RAMAD14
90 RAMAD13
89 RAMAD12
88 RAMAD11
80 RAMAD6
79 RAMAD5
78 RAMAD4
77 RAMAD3
100 VDDA1
VSSA1 Iref REFLo REFHi VREF HFIN VSSA2 AGCOUT VDDA2
1 2 3 4 5 6 7 8 9
76 RAMAD2 75 RAMAD1 74 RAMAD0 73 VSSD6 72 VDDD6 71 RAMDA0 70 RAMDA1 69 n.c. 68 RAMDA2 67 RAMDA3 66 RAMDA4 65 RAMDA5 64 RAMDA6 63 RAMDA7 62 n.c. 61 RAMRW 60 VSSD5 59 VDDD5 58 WCLK 57 BCLK 56 DATA 55 FLAG 54 SYNC 53 EBUOUT 52 V4 51 n.c. STOPCLOCK 50
85 RAMAD9
84 RAMAD8 n.c. 42
83 RAMAD7 da0 43
handbook, full pagewidth
87 RAMAD10
95 CROUT
97 MEAS1
99 VSSD9 98 VDDD9
93 VSSD8 92 VDDD8
VDDD1 10 VSSD1 11 OTD 12 MOTO1 13 n.c. 14 MOTO2/T3 15 n.c. 16 T1 17 T2 18 VDDD2 19 VSSD2 20 TEST1 21 TEST2 22 POR 23 MUXSWICH 24 n.c. 25 CL1 26 BCAIN 27 SDA 28 SCL 29 INT 30 VDDD3 31 VSSD3 32 da7 33 da6 34 da5 35 n.c. 36 da4 37 n.c. 38 da3 39 da2 40 da1 41 VDDD4 44 VSSD4 45 WRi 46 RDi 47 ALE 48 CSi 49
SAA7335
82 VSSD7 81 VDDD7
96 CFLG
94 CRIN
86 n.c.
MGK241
Fig.2 Pin configuration.
1997 Aug 11
7
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
FUNCTIONAL DESCRIPTION Analog front-end This block converts the HF input to the digital domain using an 8-bit ADC proceeded by an AGC circuit to obtain the optimum performance from the convertor. This block is clocked by ADCCLK which is set by the external crystal frequency plus a flexible clock multiplier and divider block. PLL and bit detector This subsystem recovers the data from the channel stream. The block corrects asymmetry, performs noise filtering and equalisation and finally recovers the bit clock and data from the channel using a digital PLL. The equalizer and the data slicer are programmable. Digital logic All the digital system logic is clocked from the master ADC clock (ADCCLK) described above. Advanced bit detector The advanced bit detector offers improved data recovery for multi-layer discs and contains two extra detection circuits to increase the margins in the bit recovery block: 1. Adaptive slicer: adds a second stage slicer with higher bandwidth 2. Run length 2 push-back: all T2 run lengths are pushed back to T3, thereby automatically determining the erroneous edge and shifting the transitions on that edge. Demodulator EFM/EFM+ demodulation FRAME SYNC PROTECTION CD MODE This circuit detects the frame synchronization signals. Two synchronization counters are used in the SAA7335:
SAA7335
1. The coincidence counter: this is used to detect the coincidence of successive syncs. It generates a sync coincidence signal if 2 syncs are 588 1 EFM clocks apart. 2. The main counter: this is used to partition the EFM signal into 17-bit words. This counter is reset when: a) A sync coincidence is generated b) A sync is found within 6 EFM clocks of its expected position. The sync coincidence signal is also used to generate the lock signal which will go active HIGH when 1 sync coincidence is found. It will reset to LOW when, during 61 consecutive frames, no sync coincidence is found. FRAME SYNC PROTECTION DVD MODE This circuit detects the frame synchronization signals. Two synchronization counters are used in the SAA7335: 1. The coincidence counter: this is used to detect the coincidence of successive syncs. It generates a sync coincidence signal if 2 syncs are 1488 3 EFM+ clocks apart. 2. The main counter: this is used to partition the EFM+ signal into 16-bit words. This counter is reset when: a) A sync coincidence is generated b) A sync is found within 10 EFM+ clocks of its expected position. The sync coincidence signal is also used to generate the lock signal which will go active HIGH when 1 sync coincidence is found. It will reset to LOW when, during 61 consecutive frames, no sync coincidence is found.
The 14-bit EFM (16-bit EFM+) data and subcode words are decoded into 8-bit symbols.
1997 Aug 11
8
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
Microcontroller interface The SAA7335 has two microcontroller interfaces, one serial I2C-bus and one parallel (8051 microcontroller compatible). The two communication modes may be operated at the same time, the modes are described below: 1. Parallel mode: protocol compatible with 8052 multiplexed bus: a) da0 to da7 = address/data bus b) ALE = Address Latch Enable, latches the address information on the bus c) WRi = active LOW write signal for write to SAA7335 d) RDi = active LOW read signal for read from SAA7335 e) CSi = active HIGH Chip Select signal (this signal gates the RDi and WRi signals). 2. I2C-bus mode: I2C-bus protocol where SAA7335 behaves as slave device where: a) SDA = I2C-bus data b) SCL = I2C-bus clock c) I2C-bus slave address (write mode) = 3EH d) I2C-bus slave address (read mode) = 3FH e) Maximum data transfer rate = 400 kbits/s. MICROCONTROLLER INTERFACE (I2C-BUS MODE) Bytes are transferred over the interface in single bytes of which there are two types; write data commands and read data commands.
SAA7335
The sequence for a write data command (1 data byte) is as follows: * Send START condition * Send address 3EH (write) * Write command address byte * Write data byte * Send STOP condition. The sequence for a read data command (that reads 1 data byte) is as follows: * Send START condition * Send address 3EH (write) * Write status address byte * Send STOP condition * Send START condition * Send address 3FH (read) * Read data byte * Send STOP condition. READING AND WRITING DATA TO THE SAA7335 The SAA7335 has 32 x 8-bit configuration and status registers as shown in Table 1. Not all locations are currently defined and some remain reserved for future upgrades. These can be written to or read from via the microcontroller interface using either the serial or parallel control bus.
1997 Aug 11
9
1997 Aug 11 10
Philips Semiconductors
REGISTER MAP
DSP for CD and DVD-ROM systems
Table 1
SAA7335 microcontroller register map BIT NAME R/W 7 PLL_LOCK PLL_Freq_R PLL_SET PLL_ASSYM PLL_FREQ PLL_Jit PLL_EQU PLL_Lock_In PLL_F_MEAS reserved OUTPUT1 reserved OUTPUT2 reserved OUTPUT3 reserved W R W R W R W R W R W R W R W R W R W R W R W R W R W R Lock Oride SliceBW PLL frequency (8 MSBs) jitter value (bits 9 to 2) PLL frequency (2 LSBs) reserved RL3_EN - Fmat(3 to 1) - EBU_Valid - WCLK_H_ Left - - EBU_On - Descr_On - - - Interp_On - reserved - EFM nominal setting (101110) - - WCLK_Op - - EBU control bits 28, 29 - BCLK_Op - - - Fmat (0) - - - SyncSwap (1 and 0) - - - - CD_ROM_ Scrb_On - - equalizer tap 1 equaliser tap 2 Long_Symb F_Lock In_Lock 6 Pha_Oset Integ_F0 5 4 3 PLL_Force_L PLLBW_F1 LP_BW_F3 2 1 0
ADDRESS DEC 0 1 2 3 4 5 6 7 HEX 0 1 2 3 4 5 6 7
PLL measured frequency (bits 9 to 2) PLL asymmetry value (8 bits)
EBU control bits (1 to 4) Kill Data On Kill EBU_On - -
CD_ROM_ Flag_Pin Header_On - -
8 9 10 11 12 13
8 9 A B C D
SEMA1 SEMA2 SEMA3 INTEN Status MOTOR1 SLICE1 MOTOR2 EYE_Open
general purpose semaphore register general purpose semaphore register general purpose semaphore register Preliminary specification hardware pin interrupt enable bits (map to status bits) Fl_S1 Fl_S2 Fl_S3 PLL lock DVD rdy Mot Ov Tacho reserved
SAA7335
frequency set point slice compensation value G(2 to 0) eye opening value Ki Kf
1997 Aug 11 11
Philips Semiconductors
ADDRESS NAME DEC 14 15 16 17 18 19 20 21 22 HEX E F 10 11 12 13 14 15 16 MOTOR3 MTR_F MOTO4 reserved MTR_INTG_L MTR_INTG_H CLOCKPRE SUB_C_STAT DECMODE SUB_C_DATA reserved SUB_C_End ANASET FIFOFILL_L VITSET BCA_STAT 23 24 25 17 18 19 TACHO1 BCA_DATA TACHO2 reserved TACHO3 reserved 26 27 to 31 1A 1B to 1F BCASET reserved reserved W R W R W R W R W R W R W R W R W R W R W R W R W R CL1Div ready mode subcode data (7 to 0) - AGC_En slice ON Buff_ Loaded - gain set AdDet ON sync - gain up FEndAutoS ON Buff_ORun - gain down BCLKG_En Div1 (2 to 0) busy CRC_OK err (2 to 0) motor integrator value (15 to 8) R/W 7 FIFO set point - - - SW2 - - - SW1 - - 6 5 4
BIT 3 - - 2 - - 1 - - 0 - -
DSP for CD and DVD-ROM systems
PWM_PDM OVF_SW
motor servo control (3 to 0)
motor integrator value (7 to 0)
Mux 2 reserved - AGC_On
Div2 (2 to 0) cor fail read TOC - reserved - reserved reserved -
no meaning (register read used as a signal) number of C1 frames in FIFO
tachometer multiplier frequency KTacho (7 to 0) BCA data (7 to 0) tachometer interrupt trip frequency tachometer trip (7 to 0) - - - Tacho FRes - - - - Moto2_T3 - - - - Fsam - - - - - - - - TachoInt_LF - - - - reserved - Preliminary specification servo control source - BCA_Freq (7 to 0) - - - - - - -
SAA7335
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
READING STATUS INFORMATION FROM THE SAA7335 There are several internal status signals which can be made available on the INT line (see Table 2). Table 2 Internal status signals; note 1 DESCRIPTION
SAA7335
SIGNAL Fl_S1 Fl_S2 Fl_S3 PLLlock DVDrdy MotOv Tacho Note
change in semaphore register 1 detected change in semaphore register 2 detected change in semaphore register 3 detected channel data PLL lock (not latched) indicates in-lock condition DVD header or subcode block is available, reset when SUBREADEND register is read motor overflow, (not latched) indicates when a motor overflow is occurring motor speed is higher (or lower depending on TACHO3 bit 2) than motor set point (defined in TACHO2) this signal is not latched
1. The status signal to be output is selected by interrupt control register. Subcode data/DVD header processing Q-CHANNEL PROCESSING The 96-bit Q-channel word is accumulated in an internal buffer. Sixteen bits are used to perform a Cyclic Redundancy Check (CRC). Subcode is available via the V4 output and, in addition, the Q channel code can also be read via the SUBREADDATA register. DVD HEADER The DVD header processor accumulates a selection of bytes from the beginning of the DVD sector. Two header modes are defined, one for reading the normal sector headers and one for filtering the disk physical format information (from the control data block in the lead-in area) This is controlled by the READ_TOC bit in the DECMODE register. OTHER SUBCODE CHANNELS Data of the other subcode channels (Q-to-W) may be read via the V4 pin, this is only valid in CD modes. The data on the V4 pin is clocked on the WCLK edges with a fixed delay and so may be clocked by external circuitry running off the WCLK edges, i.e. at twice the WCLK frequency.The subcode data is also available in the EBU output (DOBM) in a similar format. Crystal oscillator The crystal oscillator is a conventional 2 pin design. This oscillator is capable of operating with ceramic resonators and with both fundamental and third overtone crystals. External components should be used to suppress the fundamental output of the third overtone crystals as shown in Figs 3 and 4. Typical oscillation frequencies required are 8.462, 16.9344 or 22.57 MHz depending on the internal clock settings used and whether or not the clock multiplier is enabled. Error corrector The error corrector can operate in a number of modes; CD single-pass, CD dual-pass and DVD mode. In the CD single-pass mode the error corrector performs 2 error corrections per frame (C1 and C2). In the CD dual-pass mode up to 4 symbol corrections per frame are possible (C1-C2 then C1-C2 again). For the DVD mode full depth PI and PO error correction is performed allowing 5 corrections per PI row and full depth (2t + e) 16 correction to be performed per PO column. The error corrector also contains a flag controller. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read (after de-interleaving) by C2, to help in the generation of C2 output flags. The C2 output flags are used by the interpolator for concealment of non-correctable errors. They are also output via the EBU signal (DOBM) and the MISC output via the I2S-bus for CD-ROM applications. The flags output pin CFLG provides information on the state of all error correction and concealment flags.
1997 Aug 11
12
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
handbook, halfpage SAA7335
OSCILLATOR
CROUT 8.4672 MHz 330 100 k 22 pF 22 pF
CRIN
MGK243
Fig.3 8.4672 MHz fundamental configuration.
handbook, halfpage SAA7335
OSCILLATOR
CROUT 22.57 MHz 330 100 k 10 pF 10 pF
CRIN
3.3 H 1 nF
MGK244
Fig.4 22.57 MHz overtone configuration.
Interpolation
Hold
Interpolation
OK
Error
OK
Error
Error
Error
OK
OK
MGA372
Fig.5 Concealment mechanism.
1997 Aug 11
13
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
Audio functions CONCEALMENT A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found the last good sample is held. A 1-sample linear interpolation is then performed before the next good sample (see Fig.5). DAC Interface The SAA7335 is compatible with a wide range of ROM block decoders and Digital-to-Analog Converters DACs. The seven main formats that are supported are given in Table 3.
SAA7335
Table 3 DAC interface formats (notes 1, 2 and 3) MODE 1 2 3 4 5 6 7 Notes 1. EIAJ is the abbreviation for Electronic Industries Associated of Japan. 2. Number of BCLK periods per half WCLK period (i.e. bits per sample). 3. Clock gating must be DISABLED for format mode 7. BITS/WORD 16 16 24 24 32 32 variable FORMAT Philips I2S-bus EIAJ Philips I2S-bus EIAJ Philips I2S-bus EIAJ Philips I2S-bus
handbook, BCLK full pagewidth
DATA D0 MISC flag-MSB (1 is unreliable) WCLK SYNC
MGK245
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
flag-LSB
flag-MSB right
left
Fig.6 Philips I2S-bus data format 1 (16-bit word length).
1997 Aug 11
14
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
handbook, full pagewidth BCLK
DATA D0 MISC flag-MSB (1 is unreliable) WCLK SYNC
MGK246
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
flag-LSB
flag-MSB left
right
Fig.7 EIAJ (`S') data format 2 (16-bit word length).
BCLK handbook, full pagewidth DATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
MISC flag-MSB (1 is unreliable) WCLK SYNC
MGK247
flag-LSB
flag-MSB right
left
Fig.8 Philips I2S-bus data format 3 (24-bit word length).
BCLK handbook, full pagewidth DATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
MISC flag-MSB (1 is unreliable) WCLK SYNC
MGK248
flag-LSB
flag-MSB left
right
Fig.9 EIAJ (`S') data format 4 (24-bit word length).
1997 Aug 11
15
1997 Aug 11
BCLK DATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
Philips Semiconductors
DSP for CD and DVD-ROM systems
MISC flag-MSB (1 is unreliable) WCLK SYNC
MGK249
flag-LSB
flag-MSB right
left
Fig.10 Philips I2S-bus data format 5 (32-bit word length). 16
BCLK DATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
MISC flag-MSB (1 is unreliable) WCLK SYNC
MGK250
flag-LSB
flag-MSB left
right
Preliminary specification
SAA7335
Fig.11 EIAJ (`S') data format 6 (24-bit word length).
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
handbook, full pagewidth
variable number of clocks
BCLK DATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
FLAG flag-MSB (1 is unreliable) WCLK SYNC
MGK251
flag-LSB
flag-MSB right
left
Fig.12 Philips I2S-bus data format (variable word length).
EBU interface The biphase-mark digital output signal at pin DOBM is in accordance with the format defined by the "IEC 958" specification. Three different modes can be selected via the EBU output control register (address 1010). FORMAT The digital audio output consists of 32-bit words (subframes) transmitted in biphase-mark code (2 transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384 (see Table 4). SYNC The sync word is formed by violation of the biphase rule and therefore does not contain any data. Its length is equivalent to 4 data bits. The three different sync patterns indicate the following situations: * Sync B: start of a block (384 words), word contains left sample * Sync M: word contains left sample (no block start) * Sync W: word contains right sample.
AUDIO SAMPLE Left and right samples are transmitted alternately. VALIDITY FLAG Audio samples are flagged (bit 28 = logic 1) if an error has been detected but was non-correctable. This flag remains the same even if data is taken after concealment. USER DATA Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. CHANNEL STATUS The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is given in Table 5.
1997 Aug 11
17
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
Table 4 EBU word format WORD Sync Auxiliary Error flags Audio sample Validity flag User data Channel status Parity bit Table 5 EBU channel status WORD Consumer/professional Control BITS 0 1 to 4 always zero FUNCTION BITS 0 to 3 4 to 7 4 8 to 27 28 29 30 31 - not used; normally zero FUNCTION
SAA7335
CFLG error and interpolation flags when bit 3 of EBU control register is set to logic 1 first 4 bits not used (always zero) valid = logic 0 used for subcode data (Q-to-W) control bits and category code even parity for bits 4 to 30
copied from bits 3 to 0 of register OUTPUT2, normally should be set to a copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis always zero CD; bit 8 = logic 1, all other bits = logic 0 always zero set by OUTPUT2 control register bits 5 and 4; 00 = level II, 01 = level III always zero duty cycle corresponds with the motor not actuated, higher duty cycles mean acceleration, lower mean braking. In this mode, the MOTO2 signal is the inverse of the MOTO1 signal. Both signals change state only on the edges of a internal clock signal. Possible application diagrams are shown in Fig.13. PWM MODE, 2-LINE In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output and the motor braking signal is pulse-width modulated on the MOTO2 output. Figure 14 illustrates the PWM mode timing and Fig.15 illustrates a typical PWM mode application diagram.
Reserved Category code Reserved Clock accuracy Remaining Spindle motor control
5 to 7 8 to 15 16 to 27 28 to 29 30 to 191
The spindle motor speed is controlled by a fully integrated digital servo. Address information from the internal 8 frame FIFO and disc speed information are used to calculate the motor control output signals. Several output modes are supported: 1. Pulse density, 1-line, 2. Pulse density, 2-line (true complement output) (cannot be used with tachometer control) 3. PWM output, 2-line. The modes are selected via the motor output configuration register. PULSE DENSITY MODE In the pulse density mode the motor output (pin MOTO1) is the pulse density modulated motor output signal. A 50%
1997 Aug 11
18
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
OPERATIONAL MODES The motor servo has a number of operational modes controlled by the motor mode register MOTOR4. POWER LIMIT
SAA7335
To start and stop the spindle motor, a fixed positive or negative voltage is applied to the motor. This voltage can be programmed as a percentage of the maximum possible voltage via the motor output configuration register (MOTOR4) to limit current drain during start and stop. The following power limits are possible: * 100% of maximum (no power limit) * 75% of maximum * 50% of maximum * 37% of maximum. LOOP CHARACTERISTICS The gain and crossover frequencies of the motor control loop can be programmed via the motor gain and bandwidth register MOTOR2.
22 k MOTO1 10 nF VSS
22 k
+ -
M
+ -
VSS
MOTO2 10 nF
VDD 22 k
22 k MOTO1 22 k VSS 10 nF VSS
+ -
22 k 22 k
M
VSS
VDD
MGA363 - 1
Fig.13 Motor pulse density application diagrams.
1997 Aug 11
19
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
t rep = 45 s MOTO1 MOTO2
t dead
240 ns
Accelerate
Brake
MGA366
Fig.14 Motor 2-line PWM mode timing.
+
M 10 100 nF
MOTO1
MOTO2
VSS
MGA365 - 2
Fig.15 Motor 2-line PWM mode application diagram.
1997 Aug 11
20
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
Flags output (CFLG) (open-drain output)
SAA7335
A 1-bit flag signal is available at the CFLG pin, this contains 11 bits running off the ADCCLK, each bit period is 7 ADCCLK periods. This signal shows the status of the error corrector and interpolator and is updated every frame.
handbook, halfpage
pause
START bit
data bits
MGK252
Fig.16 Flags output format.
Table 6 Definition of flag bits BIT NUMBER 0 1 to 3 VALUE 1 000 001 010 011 100 all others reserved 4 5 9, 6 to 8 10 Notes 1. For DVD mode read PI for C1 and PO for C2. 2. This flag refers to the previous correction frame. 3. This flag refers to the previous correction frame (is not valid i.e. always logic 0 in DVD mode). 4. Bit order of root count is 9, then 6 to 8 for root count (3 to 0). ABSOLUTE TIME SYNC The sync signal is the absolute time sync signal. In the CD mode it is the FIFO-passed subcode sync and relates the position of the subcode sync to the audio data (DAC output). In the DVD mode it indicates the start of a new sector header. The flag may be used for special purposes such as synchronization of different players. root count (3 to 0) 0 core fail failure flag set because correction impossible; note 2 flag fail; note 3 this indicates the number of errors corrected; note 4 STOP bit START bit C1 first or C1 last; note 1 C2 first, CD mode reserved, DVD mode; note 1 reserved; note 1 C2 last; note 1 corrector not active; note 1 DESCRIPTION
1997 Aug 11
21
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA Vi(max) Vo(max) Io(max) Tamb Tstg VESD PARAMETER digital supply voltage analog supply voltage maximum input voltage (any input) maximum output voltage (any output) maximum output current (each output) operating ambient temperature storage temperature electrostatic handling human body model machine model Notes 1. This maximum value has an absolute maximum of 6.5 V independent of the supply voltage. note 2 note 3 -2000 -200 note 1 note 1 CONDITIONS MIN. -0.3 -0.3 -0.3 - - -20 -55
SAA7335
MAX. +6.5 +6.5 V V
UNIT
VDD + 0.5 V VDD + 0.5 V 10 +70 +125 +2000 +200 mA C C V V
2. The human body model ESD simulation is equivalent to discharging a 100 pF capacitor via a 1.5 k resistor, which produces a single discharge transient. Reference "Philips Semiconductors Test Method UZW-BO/FQ-A302 (similar to MIL-STD 883C method 3015.7)". 3. The machine model ESD simulation is equivalent to discharging a 200 pF capacitor via a resistor and series inductor with effective dynamic values of 25 and 2.5 H, which produces a damped oscillating discharge. Reference "Philips Semiconductors Test Method UZW-BO/FQ-B302 (similar to EIAJ IC-121 Test Method 20 condition C)". QUALITY This device will meet the requirements of the "Philips Semiconductors General Quality Specification UZW-BO/FQ-0601" in accordance with "Quality Reference Handbook (order number 9397 750 00192)". This details the acceptance criteria for all Q & R tests applied to the product.
1997 Aug 11
22
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
DC CHARACTERISTICS VDDD = VDDA = 5 to 5.5 V; VSSD = VSSA = 0 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDDD VDDA IDD(tot) Inputs DIGITAL INPUTS (TTL LEVEL); note 1 VIL VIH VOL VOH VI(max)(p-p) VI(nom)(p-p) DR B II(AGC) II(ADC) II(buf) II(tot) Note 1. These inputs are analog, VIL and VIH values are quoted as a guide for digital RGB users. AC CHARACTERISTICS VDDD = VDDA = 4.5 to 5.5 V; VSSD = VSSA = 0 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDDD IDDD VDDA IDDA digital supply voltage digital supply current analog supply voltage analog supply current VDDA = 5 V VDDD = 5 V 4.5 - 4.5 - 5.0 60 5.0 60 5.5 165 5.5 165 PARAMETER CONDITIONS MIN. TYP. LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage - 2.0 0.8 - - - 41 0 to 12 dB gain 12 to 20 dB gain AGC input current ADC input current output buffer input current total input current - - - - - - - - - - - 1 - - - 1 24 3 - 0.8 - - 2.4 digital supply voltage analog supply voltage total supply current at 25 MHz clock 4.5 4.5 - - - 60 5.5 5.5 - PARAMETER CONDITIONS MIN. TYP.
SAA7335
MAX.
UNIT
V V mA
V V V V
ANALOG INPUTS maximum input voltage (peak-to-peak value) nominal input voltage (peak-to-peak value) dynamic range -3 dB bandwidth 2 - - - - - - - 28 V V dB MHz MHz mA mA mA mA
MAX.
UNIT
V mA V mA
1997 Aug 11
23
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog front-end (VDDA = 4.5 to 5.5 V); HFIN fchan VIL VIH ILI Ci VOL IOL CL to(f) VOL VOH CL to(r) to(f) ILI(Z) VOL VOH CL to(r) to(f) ILI(Z) channel frequency - - 2.0 Vi = 0 to VDDD -10 - - - - - - - - - - - - - - - - - - - - - - 50 MHz
Digital inputs LOW-level input voltage HIGH-level input voltage input leakage current input capacitance 0.8 - +10 10 V V A pF
Open-drain output; pin INT LOW-level output voltage LOW-level output current load capacitance output fall time CL = 20 pF; note 1 IOL = 0 mA IOH = -8 mA CL = 20 pF; note 1 CL = 20 pF; note 1 Vi = 0 to VDDD IOL = 1 mA 0 - - - 0.4 0 50 15 V mA pF ns
3-state outputs LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time 3-state leakage current 0 2.4 - - - -10 0.4 - 50 15 15 +10 V V pF ns ns A
3-state outputs; pins MOTO1, MOTO2 and DOBM LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time 3-state leakage current CL = 20 pF; note 1 CL = 20 pF; note 1 Vi = 0 to VDDD VDDD = 4.5 to 5.5 V; 0 IOL = 10 mA VDDD = 4.5 to 5.5 V; -1 IOH = -10 mA - - - -10 0.8 +2.4 50 10 10 +10 V V pF ns ns A
Digital input/outputs (VDDD = 4.5 to 5.5 V) INPUT/OUTPUT: SDA (INPUT/OPEN-DRAIN I2C-BUS OUTPUT) VIL VIH VOL IOL CSDA CSCL NmarL NmarH LOW-level input voltage HIGH-level input voltage LOW-level output voltage LOW-level output current serial data line capacitance serial clock line capacitance LOW-level noise margin HIGH-level noise margin IOL = 2 mA; Isink = 3 mA - 3.0 - - - - - - - - - - - - 0.1VDDD 0.2VDDD 1.5 - 0.4 - 10 10 - - V V V mA pF pF
1997 Aug 11
24
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
SYMBOL Rs Cbus(max) VIL VIH ILI Ci gm Ro Ci ILI fxtal Cfb Co
PARAMETER series resistance on the SDA and SCL lines maximum bus capacitance
CONDITIONS - per wire -
MIN.
TYP. 300 400 - - - - - -
MAX.
UNIT pF
INPUT: SCL (CMOS INPUT) LOW-level input voltage HIGH-level input voltage input leakage current input capacitance Vi = 0 - VDDD -0.3 0.7VDDD -10 - - - - -10 0.3VDDD +10 10 - - 10 +10 - 5 10 V A pF VDDD + 0.3 V
Crystal oscillator input CRIN (external clock) mutual conductance at start-up output resistance at start-up input capacitance input leakage current 4 11 - - mS k pF A
Crystal oscillator output CROUT (see Figs 3 and 4) crystal frequency feedback capacitance output capacitance 4 - - 25 - - MHz pF pF
I2S-bus timing CLOCK OUTPUT SCLK (see Fig.17) Tcy tSCLKH output clock period clock HIGH time set by CLKPRE1 register - - - - tSCLKL clock LOW time - - - tsu(SCLK) set-up time - - - th(SCLK) hold time - - - 472.4 - - - - - - tbf tbf tbf tbf tbf tbf - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns
1997 Aug 11
25
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
SYMBOL
PARAMETER
CONDITIONS - - - - - - - - -
MIN.
TYP. - - - - - - - - -
MAX.
UNIT
External RAM timing (see Figs 18 and 20) tAV-DV tOE-DV tW(W) tsu(A) th(A) tsu(D-EW) th(D-EW) tOE-DA tOD-DI address valid to data valid output enable to data valid write pulse width address set-up before start of write address hold after end of write data set-up to end of write data hold after end of write output enable to data active output disable to data inactive tbf tbf tbf tbf tbf tbf tbf tbf tbf ns ns ns ns ns ns ns ns ns
Microcontroller interface timing (see Figs 18 and 20) INPUT ALE tsu(A-ALE) th(A-ALE) tALEL tALEH td(ALEL-WRL) tr tf tIL(R/W) tIH(R/W) tr tf READ MODE td(RLDV) td(RHDX) WRITE MODE tsu(QVWX) th(WHQX) Notes 1. Timing reference voltage levels are 0.8 V and VDDD - 0.8 V. 2. Negative set-up time means that data may change after clock transition. 1997 Aug 11 26 set-up time WR LOW to DA0 to DA7 hold time WR HIGH to DA0 to DA7 3-state - - - - ns ns delay time RD LOW to DA0 to DA7 valid delay time RD HIGH to DA0 to DA7 high-impedance 2 x ADC - CLK + 35 15 - - - ns ns address set-up before ALE LOW address hold after ALE LOW input LOW time input HIGH time delay time ALE LOW to WR LOW rise time fall time 25 25 - - - - - - - - 240 - - - 240 ns ns ns ns ns ns ns
1 x ADC - CLK + 15 1 x ADC - CLK + 15 - - - - - -
INPUTS RDI AND WRI input LOW time input HIGH time rise time fall time 1 x ADC - CLK + 15 1 x ADC - CLK + 15 - - - - ns ns ns ns
2 x ADC - CLK + 25
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
Tcy tSCKL tSCLKH V DD - 0.8 V SCLK 0.8 V th(SCLK) WCLK DATA MISC tsu(SCLK) V DD - 0.8 V 0.8 V
MGL507
Fig.17 I2S-bus timing.
handbook, full pagewidth
tALEL
tALEH
ALE 3 RDi th(A-ALE) tsu(A-ALE) DA0 to DA7 A0 to A7 9 td(RLDV) DATA OUT td(RHDX) 13
MGK253
tIH(R/W)
Fig.18 Microcontroller interface timing; parallel read mode.
1997 Aug 11
27
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
handbook, full pagewidth
ALE
td(ALEL-WRL) WRi
tIH(R/W)
tsu(QVWX) tsu(A-ALE) th(A-ALE) th(WHDX) DATA IN 9
MGK254
DA0 to DA7
A0 to A7
Fig.19 Microcontroller interface timing; parallel write mode.
handbook, full pagewidth
tW(W)
WE tOE-DV OE
ADDRESS
A0 tsu(A)
A1 th(A) D1 tsu(D-EW) tsu(D-EW)
A2 tOE-DA X tAD-DV D2 tOD-DI
A3
A4
DATA
D1
MBH995
write cycle
read cycle
write cycle
Fig.20 External RAM timing.
1997 Aug 11
28
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
APPLICATION INFORMATION
SAA7335
The complete data path chipset consists of two ICs, the CD decoder (or DSP) device and the block decoder/host interface manager. In addition to these components a general purpose microcontroller and tracking servo is necessary to produce a complete controller system for a DVD mechanism. The DSP, block decoder and microcontroller are shown highlighted in Fig.21. An ADC application circuit is illustrated in Fig.22.
handbook, full pagewidth MECHANISM/SERVO
SUBSYSTEM
DECODER/DATA PATH SUBSYSTEM
RAM BUFFER audio L/R output
AUDIO DAC
laser spindle motor SLED/FOCUS ACTUATORS
PREAMPLIFIER
CD-DSP DEMODULATION C1-C2 ERROR CORRECTOR
SERVO CONTROL PD TRACKING (3 BEAM OPTIONAL FOR BACKWARD CD-ROM COMPATIBILITY)
BLOCK DECODER (FOR CD-ROM COMPATIBILITY) AND HOST INTERFACE
PC host interface
RAM BUFFER SYSTEM CONTROLLER
MGK255
user key switches
Fig.21 Basic DVD player block diagram.
1997 Aug 11
29
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
handbook, full pagewidth
VCC
TP1
97 98
R14 4.7 C11 47 F (50 V) C10 100 nF
99 100 1 2 3 C18 22 nF C19 47 F (50 V) TP6 R28 100 k 4
SAA7335
5 C17 22 nF
6
7
8
9
R29 AGND1 10 k AGND1 X6 HF input 2.2 nF AGND1 C16
TP5
AGND1
VCC R25 4.7 C14 100 nF
MGK256
C15 47 F (50 V)
Fig.22 ADC application circuit.
1997 Aug 11
30
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SAA7335
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
ISSUE DATE 95-12-19 97-08-04
1997 Aug 11
31
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
SAA7335
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Aug 11
32
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7335
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF CD/DVD DEVICES Supply of this CD/DVD IC does not convey an implied license under any patent right to use this IC in any CD or DVD application. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Aug 11
33
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
NOTES
SAA7335
1997 Aug 11
34
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
NOTES
SAA7335
1997 Aug 11
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/01/pp36
Date of release: 1997 Aug 11
Document order number:
9397 750 01764

▲Up To Search▲

Price & Availability of SAA7335

	To Download SAA7335 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .